1. Field of the Invention
Embodiments relate to the field of device manufacturing. More particularly, the present invention relates to a method, system and structure for performing implantation in a CMOS device.
2. Discussion of Related Art
As semiconductor devices such as CMOS devices scale to smaller dimensions, increased contact resistance to source/drain (S/D) areas is becoming an increasing challenge, especially for the 32 nm technology node and below. Contacts to S/D regions in advanced CMOS devices are typically formed using a metallic silicide contact that forms on a semiconductor region of the source/drain. As devices continue to scale to smaller dimensions and channel dimensions continue to shrink, the contact resistance (Rc) between silicide and doped S/D constitutes a larger and larger fraction of the overall parasitic resistance. Factors contributing to the S/D contact resistance include the active dopant concentration in the S/D region at the interface between the semiconductor and the metallic contact, and the Schottky barrier height existing between the metallic contact and doped semiconductor.
Because reducing Schottky barrier height results in a reduction of the overall contact resistance, extensive research has been conducted to study materials and processes for lowering the barrier height. Recently, the implantation of novel species such as sulfur, aluminum, selenium, and several other species has been demonstrated to reduce the Schottky barrier height between silicide and the S/D regions in Si-based MOS devices.
FIG. 1 depicts a known implantation scheme for lowering contact resistance in CMOS devices. The substrate 10 includes an n-type field effect transistor (NFET) 12 and a p-type field effect transistor (PFET) 14 region, which are subjected to implanting ions 16. The ions 16 are introduced into CMOS device 10 in S/D regions in a manner in which ions accumulate at or near the interface between silicide contact 18 and doped semiconductor region 20. However, prior art studies have found that implantations may produce different, sometimes opposite, effects on device properties for PMOS devices as opposed to NMOS devices. For example, a given ion species implanted at a first dose and first energy may improve NFET performance, while degrading PFET performance.
In order to address this problem, it may be desirable to tailor interface implants for NFETs and PFETs separately, so that the appropriate implantation species/dose/energy for enhancing Rc in the PFET can be introduced only into the PFET, and the appropriate implantation species/dose/energy for enhancing Rc in the NFET can be introduced only into the NFET. In order to protect the NFET device while performing the PFET implant, the NFET region may be masked, as depicted in FIG. 2. As further depicted therein, ions 26 are directed to a substrate 10 while the NFET 12 is protected by a mask 22, which may be photoresist. The PFET 14 receives ions 26, which are designed to reduce Rc in PFET 14. A converse implantation procedure may be performed, in which the PFET 14 is masked while the NFET 12 is unmasked. The ions employed in the latter procedure are designed to reduce Rc in NFET 12. Thus, in order to optimize interface-modification implants for PFETs and NFETs separately, the extra masking steps required may entail significant additional time and expense. It will be appreciated, therefore, that improvements are desirable in present day methods for lowering device contact resistance.